1. Field of the Invention
This invention relates generally to a clock generator, and more specifically, a digital device for phase shifting the clock signal.
2. Description of the Related Art
A clock signal is a steady stream of timing pulses used, for example, to synchronize multiple devices of a system. Some devices may use a clock signal that has a different phase than the clock signal of the system. Typically, the phase of the clock signal is shifted using an analog phase-locked loop (xe2x80x9cPLLxe2x80x9d) circuit. A disadvantage of using the analog PLL circuit to shift the phase of the clock signal is that the analog PLL circuit design is dependent on the foundry that produces that circuit on the silicon chip. That is, the design of the PLL circuit used to achieve a desired phase shift varies from foundry to foundry. Because of this dependence, a different analog PLL circuit design may have to be developed in order to achieve the desired phase shift when moving from one foundry to another. Another disadvantage is that the analog PLL circuit is mainly composed of resistors and capacitors and these resistors and capacitors occupy a substantial area of the chip given the present integrated-circuit fabrication technology. The analog PLL circuit is also susceptible to noise.
The phase shift may also be accomplished using a digital circuit. Compared to the analog circuit, the clock phase shift produced by a digital circuit provides less variations when moving from one foundry to another. Also, the digital circuit occupies less area on the chip than the analog PLL circuit. The disadvantage of using the digital circuit is that the phase shift it produces is affected by temperature changes and voltage variations. These operating condition variations cause the resulting phase shift to differ from the desired phase shift.
For the foregoing reasons, it is desirable to have a clock signal phase shift system that is foundry independent, provides accurate phase shifting regardless of operating conditions (e.g., excessive noise, and temperature and voltage variations), and occupies a smaller area on the chip than the analog PLL circuit.
According to an embodiment of the present invention, a method is described to shift the phase of a clock signal by a desired phase shift amount. This method includes generating multiple phase shifted clock signals and then determining a particular one of the multiple phase shifted clock signals that provides the desired phase shift amount.
According to an embodiment of the present invention, a system to shift the phase of a clock signal by a desired phase shift amount is described. This system includes a phase shift determination unit to generate multiple phase shifted clock signals and to determine a particular one of the multiple phase shifted clock signals that provides the desired phase shift amount.
According to an embodiment of the present invention, a system to shift the phase of a clock signal by a desired phase shift amount is described. This system includes multiple delay units, each of the multiple delay units are coupled together to form a chain. The multiple delay units shift the clock signal multiple times to generate the multiple phase shifted clock signals. This system also includes multiple memory devices, each of the multiple memory devices are coupled to a corresponding one of the multiple delay units. The multiple memory devices store multiple clock characteristics of the clock signal when triggered by the multiple phase shifted clock signals. A phase selection table indicates a particular one of the multiple delay units that provides a particular one of the multiple phase shifted clock signals that has the desired phase shift amount. Also included is a phase selection controller that is coupled to the multiple memory devices and the phase selection table. The phase selection controller processes the multiple clock characteristics to find the particular one of the plurality of phase shifted clock signals that has the desired phase shift amount.